1. Field of the Invention
The present invention relates to a semiconductor apparatus and a manufacturing method of the same, more particularly, the semiconductor apparatus of which reliability of interconnections is improved and the manufacturing method of the same, the interconnections are formed by using the damascene process.
2. Description of the Related Art
In recent years, the miniaturization of the interconnections and the multi-level interconnection are being carried according to the high integration of the semiconductor apparatus and the miniaturization of the semiconductor chip. The process, which is so-called damascene method (process), is generally used for forming the multi-level interconnection structure. This damascene method, which forms interconnections and vias, includes three steps. The first step is to form a via hole or a trench in an insulation film. The second step is to form a conductive film on the surface of the insulation film, in and above the via hole or the trench. The third step is to polish the conductive film on the surface of the insulation film and above the via hole or the trench by the chemical mechanical polish method (CMP: Chemical Mechanical Polishing). This method is suitable for forming the multi-level interconnection made from conductive materials which includes copper, even though copper is difficult to etching.
The conventional damascene process will be described with reference to drawings. FIGS. 1A to AC are sectional views showing the part of the conventional damascene process.
Firstly, as shown in FIG. 1A, a first etch stopping film 102 such as SiN and a first inter-level dielectric 103 such as SiO2 are formed by this order on a substrate 101 on which MOS transistors and the like are formed. Next, a resist pattern is formed on the first inter-level dielectric 103 as a mask for a conventional dry etching method. Then, a first trench 103a is formed by etching the first inter-level dielectric 103 and the first etch stopping film 2 by using the conventional dry etching method. Next, a first barrier metal film 104 of TiN is formed on the first inter-level dielectric 103 and in the first trench 103a. 
In this situation shown in FIG. 1A, a seed metal (not shown) of Cu is formed on the first barrier metal film 104 by the sputtering method. The first barrier metal film 4 prevents the diffusion of the interconnection material. The seed metal facilitates the plating growth of Cu which is used for the interconnection. Then, a Cu 105 is formed by the electrolysis plating method on the seed metal. This situation is show in FIG. 1B.
In this situation, the Cu 105 and the barrier metal film 104 on the first inter-level dielectric 103 are removed by the CMP method. As a result, a first Cu interconnection 105a is formed in the first trench 103a. This situation is show in FIG. 1C.
After that, by repeating processes similar to the above-mentioned, a semiconductor apparatus with the desirable multi-level interconnections is obtained.
The multi-level interconnection of Cu can be formed by the above-mentioned damascene method. However, in this method, the adhesiveness between Cu, which is the interconnection material, and TiN, which is the barrier metal, is not always good enough. Therefore, the degradation problem arises in the electromigration tolerance.
The technique of a semiconductor apparatus and a manufacturing method of the same related to this problem is disclosed in Japanese Laid Open Patent Application (JP-A, 2000-77413). In this patent application, the structure to make barrier metal composed of Al intervene between Cu and TiN is disclosed to solve the problem.
Hereinafter, the technique of the above-mentioned conventional patent application (hereinafter referred to as “the patent application” is concretely explained. FIGS. 2A to 2C are sectional views showing the part of the conventional damascene process. As shown in FIG. 2A, first, an under layer barrier metal film 118a composed of TiN is formed on a first inter-level dielectric 103 and in a first trench 103a which was formed in the first inter-level dielectric 103. Next, an upper layer barrier metal film 118b composed of Al is formed on the under layer barrier metal film 118a. After that, a Cu 105 is formed on the upper layer barrier metal film 118b by the plating method as shown in FIG. 2B. Then, a first Cu interconnection 105a is formed by polishing the under layer barrier metal film 118a, the upper layer barrier metal film 118b and the Cu 105 on the first inter-level dielectric 103 by the CMP method as shown in FIG. 2C. By forming barrier metals having the layered structure, the adhesiveness between Cu and barrier metal can be improved. Then, by restraining the movement of Cu atoms, the Cu interconnection which has high electromigration tolerance can be formed.
However, as the progress of the miniaturization of the interconnections, there is a problem that it becomes difficult for Cu to be buried in the dielectric by the method of the patent application mentioned above.
Generally, when the trench width and the via hole diameter are being small and the aspect ratio (the trench depth/the trench width or the via hole depth/the via hole diameter) is being big, it becomes difficult for Cu to be buried.
In case of the patent application mentioned, after forming the trench and the via hole, the upper layer barrier metal film 118b composed of Al is formed in addition to the under layer barrier metal film 118a composed of TiN in the method. Therefore, the margin of Cu being buried becomes small because of the width of the upper layer barrier metal film 118b. As a result, as shown in FIG. 3A, a void defect 119 is formed in the trench or the via hole in the Cu 105 at the step of Cu being buried. Or, the trench and the via hole have been filled with Al when a film thickness of the upper layer barrier metal film 118b becomes equal to or more than ½ of the width of the trench and the diameter of the via hole. Moreover, there is a problem that the equipment, which has an enough property of Cu being buried, becomes necessary to form the upper layer barrier metal film 118b uniformly in the minute trench and the minute via hole.
Also, as the progress of the miniaturization of the interconnections, another problem arises in the reliability of the interconnection in addition to the problem of the degradation of the property of interconnection being buried. That is, the reliability of the interconnection is decreased because the void defect is generated after the interconnections forming.
Generally, the grain size of Cu depends on the width of the interconnection and the diameter of the via. In the interconnection with the wide width, the grain size tends to be big. On the other hand, in the interconnection with the fine width and in the via with fine diameter, the grain size tends to be small. The difference with grain size is equivalent to the difference with entropy. Then, when the heat-treatment is done to the interconnection and the via each of which has different grain size, material moves to balance entropy. Therefore, the transportation phenomenon occurs, which Cu in the fine interconnection and the fine via is sucked by the wide interconnection with low entropy.
This transportation phenomenon is explained with reference to FIG. 3B. As for the grain size in the via, the entropy is big because the grain size is small. On the other hand, as for the grain size in the interconnection, the entropy is small because the grain size is big. As a result, Cu atoms in the via has moved to the interconnection to balance entropy when the heat-treatment is done after the interconnection forming. So, the void defect 119 occurs in the via and the connection reliability of the interconnection has decreased.
In the damascene method which forms Cu interconnection using the CMP method, when the interconnection forming, it is important to restrain the occurrence of the void defect which accompanies the degradation of the property of the interconnection being buried in the trench. In the method of the patent application above-mentioned, these problems can not be solved.